1. Field of the Invention
The present invention relates to a nonvolatile memory Device provided with a rewritable nonvolatile memory, a memory controller for controlling this device, a nonvolatile memory System, and a data writing method.
2. Discussion of the Related Art
Demand for a nonvolatile memory Device provided with a rewritable nonvolatile main storage memory has been expanding primarily in the field of a semiconductor memory card. The memory card is provided with a flash memory as the nonvolatile memory and a memory controller for controlling it. The memory controller is designed to execute reading and writing controls for flash memories according to reading and writing instructions given by an access device such as digital still camera, personal computer or the like. With the flash memory, writing errors occur relatively frequently since characteristics of storage elements are quite-variable compared to those of volatile memories such as RAM. To overcome this inconvenience, some memory cards incorporating a nonvolatile memory perform alternative processing to replace a storage area where writing error occurred with other storage area (Japanese Unexamined Patent Publication No. 2003-76615). In this disclosure, for the nonvolatile flash memory, a flash memory in which each memory cell is closed in one page as represented by binary NAND is normally employed.
In the meantime, high expectations are placed on multiple-valued NAND flash memories to be used as low-cost flash memories and it is more likely that flash memories of this sort will become main stream of main storage memory for the memory card in the future. Japanese Unexamined Patent Publication No. 2001-93288 discloses a technology in which page structure of multiple-valued NAND flash memory is improved for the sake of realization of high-rate access. Conventional flash memory which is of binary memory type is designed in such that one memory cell holds a data of a certain bit in one page. On the other hand, multiple-valued NAND flash memory is configured in such that each memory cell lies astride over a plurality of pages, for example two pages, that is, holds a plurality of bits data.
FIGS. 1 to 3 are block diagrams showing nonvolatile memories in which each memory cell are configured lying astride over a plurality of pages as the multiple-valued NAND flash memory. In FIGS. 1 to 3, pages bearing the same page group number (GN) are two pages in which data being held by one memory cell is contained. A page without hatching is referred to as the first page and a page with diagonal hatching is referred to as the second page.
For example, a multiple-valued NAND flash memory depicted in FIG. 1 constitutes one memory cell while an even number page and an odd number page form a pair. The group number identified by GN in the drawings is a page pair in which the same page shares one memory cell. In each of page pairs, a page with lower order of address is set to be the first page and a page with higher order (a page with hatching) is set to be the second page. In FIG. 1, the first page and the second page are adjoining while the first page and the second page are separated in FIGS. 2 and 3. This is because they are isolated in order to reduce effects (disturbance) upon data stored in one page by writing into the other page.
However, when one memory cell is constituted lying astride over two pages, there is such a problem that if an error occurs in writing into the one page, the data stored in the other page will be changed. This problem will be discussed hereafter referring to FIGS. 4 to 6.
FIG. 4 is a characteristics diagram showing voltage distribution of a memory cell of multiple-valued NAND flash memories shown in FIGS. 1 to 3. This memory cell stores information of 2 bits. A horizontal axis represents voltage V obtained from the memory cell and a vertical axis represents probability P to attain the voltage.
Now, in four distributions shown in FIG. 4, codes “11”, “10”, “00” and “01” are assigned from the left. A right digit (bit) of each code corresponds to a first page and a left digit (bit) corresponds to a second page. Each memory cell is expressed as “11” in erased state. When writing is attempted to the first page from this state, and writing is made normally, each memory cell remains in “11” state or changes from “11” state to “10” state. After that, when writing is attempted to the second page, and writing is made normally, each memory cell remains from “11” state to “11” state or changes to “01” state. Otherwise, it remains from “10” state to “10” state or changes to “00” state.
FIG. 5 is a characteristics diagram showing a state writing into a memory cell has been normally completed. In FIG. 5, it is assumed that information “01” that is a target value is written by writing into the first page and the second page. As for writing step, first “11” state is obtained by writing into the first page and “01” state is obtained by writing into the second page.
FIG. 6 is a characteristics diagram showing a state when writing into memory cell has failed to be completed normally. FIG. 6 illustrates such a case, when writing into the second page, in a step applied voltage to a memory cell is changed from “11” state to “01” state, it is put into “10” or “00” state due to trouble such as voltage variation within the flash memory. Hereinafter, this is referred to as “flash trouble”. Further, when writing into the second page, in a step applied voltage to the memory cell is changed from “11” state to “01” state, there is such a case power supply to be supplied to the nonvolatile memory is turned OFF at a point of time when the voltage reached “10” or “00” state, and the state results in “10” or “00”. Hereinafter, this is referred to as “Power shutdown”.
Further, with the memory card, since the power is normally supplied from an access device side, if the power supply for the access device is turned OFF carelessly under writing data or the memory card is forcibly taken out from the access device, a power shutdown will occur.